`include "../../src/ALU.v"
`timescale 1ps/1ps

module testbench;
    reg clk;
    initial clk = 1;
    always #5 clk = ~clk;

    reg reset;
    initial reset = 0;

    reg[3:0] ALUcontrolOut;
    reg[31:0] data1, data2;
    wire ifZero;
    wire[31:0] ALUresult;

    parameter addOP = 4'b0010;
    parameter subOP = 4'b0110;
    parameter andOP = 4'b0000;
    parameter orOP  = 4'b0001;
    parameter errorOP = 4'b1111;

    initial
    begin
        #10
            ALUcontrolOut = subOP;
            data1 = 32'd10;
            data2 = 32'd20;
        #10
            $stop;
    end

    ALU u0(clk, reset, ALUcontrolOut, data1, data2, ifZero, ALUresult);

    initial
    begin
        $dumpfile("test.lxt");
        $dumpvars;
    end


endmodule